A goal of the electronics industry is to provide reliable electrical connections between electronic circuit components, while compensating for dimensional irregularities arising from the manufacture of those components or subcomponent assemblies. For example, conductive pads on electronic components or metal traces on circuit boards do not always lie in the same plane, thus creating non-uniform spacing between mated components and incomplete electrical connection.
Current electrical connection technology uses a solder attachment process (BGA, microBGA, C-4) to make electrical interconnects from integrated circuit (IC) packages to printed wiring boards, and an underfill material that flows and fills the spaces between the solder interconnects. The underfill material acts to hold the board and package in compression. Underfilled assemblies are capable of surviving thermal aging, heat and humidity aging or pressure pot testing. However, current underfill materials are expensive and have long cure times. They require freezer storage, have short working times, and do not consistently and reliably fill 100% of the void spaces under a chip, which often occurs through capillary action to flow and fill.
Existing metallurgical interconnect components involve placing solder balls or bumps on conductive pads of one electrical component, for connection to another electrical component, such as, chips to circuit boards, circuit boards to circuit boards, multichip modules to circuit boards or terminals to terminal connectors. Unfortunately, a very large number of solder bump connections are required, since one bump is required for each contact point or bonding pad on each die. As is known in the art, solder bump interconnections are susceptible to thermal stress cracking and are a significant source of failure.
A disadvantage of the existing solder bump methodology is that it requires the presence of metal, i.e., the solder, above active circuitry, thus slowing electrical signal propagation. Further, existing solder bump technology requires relatively large attachment sites and cannot be inspected after reflow of the solder.
Another disadvantage with existing solder bump techniques is that shadow masks are required. The masks, which are often made of molybdenum, are expensive and must be replaced periodically. After each use, the masks must be cleaned to remove solder from the mask. A disadvantage of this process is the high overall cost of the process. Also, the quality and reuse of the solder alloy is not acceptable and masks get coated with the solder materials and must be continuously cleaned or replaced.
Another problem with existing bump technology is that the height of the solder bump creates a very narrow gap between the semiconductor chip and the substrate, approaching less than 50 microns, which cannot be adequately underfilled by using existing underfill techniques.
In an attempt to overcome some of these disadvantages, an interconnect sheet has been proposed in U.S. Pat. No. 5,576,519 to Swamy. There, a polymeric sheet is predrilled to form openings which are filled with solder paste and reflowed to form solid solder columns. As such, the compliancy of the interconnect sheet is not extended to the solder columns since they are solid in design.
Thus, a need exists for a compliant material that can provide uniform quantities of solder for connecting electronic components while providing a compliant substrate that compensates for irregularities in surface geometry, such as that caused by the lack of planarity in the conductive pads or metal circuit traces.